Enumerated Types

Enumerated types for DMA driver. More...

Enumerations
enum	dma_state_en {   DMA_INSTANCE_INITIALIZED = 0 ,   DMA_INSTANCE_NOT_INITIALIZED = 1 }
	DMA instance state indicators. More...
enum	dma_transfer_mode_en {   DMA_TRANSFER_MODE_1D = 0 ,   DMA_TRANSFER_MODE_2D = 1 }
	DMA transfer modes. More...
enum	dma_operation_type_en {   DMA_OP_DISABLE = 0 ,   DMA_OP_CONTINUE = 1 ,   DMA_OP_WRAP = 2 ,   DMA_OP_FILL = 3 }
	DMA operation types (maps to hardware XTYPE/YTYPE fields) More...
enum	dma_security_en {   DMA_SECURITY_SECURE = 0 ,   DMA_SECURITY_NON_SECURE = 1 }
	DMA security attributes. More...
enum	dma_privilege_en {   DMA_PRIVILEGE_PRIVILEGED = 0 ,   DMA_PRIVILEGE_UNPRIVILEGED = 1 }
	DMA privilege attributes. More...
enum	dma_unit_size_en {   DMA_UNIT_SIZE_1BYTE = 0 ,   DMA_UNIT_SIZE_2BYTES = 1 ,   DMA_UNIT_SIZE_4BYTES = 2 ,   DMA_UNIT_SIZE_8BYTES = 3 ,   DMA_UNIT_SIZE_16BYTES = 4 }
	DMA transfer unit sizes (maps to hardware TRANSIZE field) More...
enum	dma_burst_size_en {   DMA_BURST_SIZE_1 = 0 ,   DMA_BURST_SIZE_2 = 1 ,   DMA_BURST_SIZE_4 = 2 ,   DMA_BURST_SIZE_8 = 3 ,   DMA_BURST_SIZE_16 = 4 }
	DMA burst lengths (maps to hardware MAXBURSTLEN field) More...
enum	dma_fifo_depth_en {   DMA_FIFO_DEPTH_1 = 0 ,   DMA_FIFO_DEPTH_2 = 1 ,   DMA_FIFO_DEPTH_4 = 2 ,   DMA_FIFO_DEPTH_8 = 3 ,   DMA_FIFO_DEPTH_16 = 4 ,   DMA_FIFO_DEPTH_32 = 5 ,   DMA_FIFO_DEPTH_64 = 6 ,   DMA_FIFO_DEPTH_128 = 7 ,   DMA_CHANNEL_FIFO_DEPTH_ANY = 0xFF }
	DMA FIFO depths (extensible for future hardware) More...
enum	dma_reg_reload_type_en {   DMA_REG_RELOAD_DISABLED = 0 ,   DMA_REG_RELOAD_SIZE_ONLY = 1 ,   DMA_REG_RELOAD_SRC_ADDR_AND_SIZES = 3 ,   DMA_REG_RELOAD_DEST_ADDR_AND_SIZES = 5 ,   DMA_REG_RELOAD_ALL_ADDR_AND_SIZES = 7 }
	DMA register reload types (maps to hardware AUTOCFG register) More...
enum	dma_trigger_target_en {   DMA_TRIGGER_SOURCE = 0 ,   DMA_TRIGGER_DEST = 1 }
	DMA trigger targets. More...
enum	dma_sw_trigger_type_en {   DMA_SW_TRIG_SINGLE = 0 ,   DMA_SW_TRIG_LAST_SINGLE = 1 ,   DMA_SW_TRIG_BLOCK = 2 ,   DMA_SW_TRIG_LAST_BLOCK = 3 }
	DMA software trigger types (maps to hardware CMD register fields) More...
enum	dma_trigger_type_en {   DMA_TRIG_SW_REQ = 0 ,   DMA_TRIG_RESERVED = 1 ,   DMA_TRIG_HW_REQ = 2 ,   DMA_TRIG_INTERNAL_REQ = 3 }
	DMA trigger types. More...
enum	dma_status_flags_en {   DMA_STATUS_DONE = (1U << 0) ,   DMA_STATUS_ERROR = (1U << 1) ,   DMA_STATUS_DISABLED = (1U << 2) ,   DMA_STATUS_STOPPED = (1U << 3) ,   DMA_STATUS_PAUSED = (1U << 4) ,   DMA_STATUS_BUSY = (1U << 5) ,   DMA_STATUS_WAITING = (1U << 6) }
	DMA status flags (maps to hardware CH_STATUS register) More...
enum	dma_interrupt_flags_en {   DMA_INT_DONE = (1U << 0) ,   DMA_INT_ERROR = (1U << 1) ,   DMA_INT_DISABLED = (1U << 2) ,   DMA_INT_STOPPED = (1U << 3) }
	DMA interrupt flags. More...
enum	dma_status_en {   DMA_OK = 0 ,   DMA_ERROR_INVALID_INSTANCE = 1 ,   DMA_ERROR_INVALID_CHANNEL = 2 ,   DMA_ERROR_INVALID_CONFIG = 3 ,   DMA_ERROR_CHANNEL_BUSY = 4 ,   DMA_ERROR_NO_CHANNELS = 5 ,   DMA_ERROR_HARDWARE_ERROR = 6 ,   DMA_ERROR_INVALID_ADDRESS = 7 ,   DMA_ERROR_INVALID_SIZE = 8 ,   DMA_ERROR_BURST_MISMATCH = 9 ,   DMA_ERROR_ALIGNMENT = 10 ,   DMA_ERROR_TEMPLATE_NOT_SUPPORTED = 11 ,   DMA_ERROR_2D_NOT_SUPPORTED = 12 ,   DMA_ERROR_TRIGGER_CONFLICT = 13 ,   DMA_ERROR_INVALID_PARAMETER = 14 ,   DMA_ERROR_ALREADY_INITIALIZED = 15 ,   DMA_ERROR_NOT_INITIALIZED = 16 ,   DMA_ERROR_SEMAPHORE_ALLOC = 17 ,   DMA_ERROR_MEMORY_ALLOC = 18 ,   DMA_ERROR_TRANSFER_FAIL = 19 }
	DMA error codes. More...
enum	dma_transfer_options_en {   DMA_OPTION_NONE = 0 ,   DMA_OPTION_HIGH_PRIORITY = 1 ,   DMA_OPTION_SECURE = 4 ,   DMA_OPTION_PRIVILEGED = 8 }
	DMA transfer options for simple API. More...
enum	dma_transfer_type_en {   DMA_TRANSFER_TYPE_MEM2MEM = 0 ,   DMA_TRANSFER_TYPE_PERIPH2MEM ,   DMA_TRANSFER_TYPE_MEM2PERIPH ,   DMA_TRANSFER_TYPE_STATIC }
	DMA transfer types. More...
enum	dma_trigger_mode_en {   DMA_TRIG_MODE_COMMAND = 0 ,   DMA_TRIG_MODE_RESERVED = 1 ,   DMA_TRIG_MODE_FLOW = 2 ,   DMA_TRIG_MODE_INTERNAL = 3 }
	DMA software trigger modes (maps to trigger mode field in hardware) More...
enum	dma_donetype_en {   DMA_DONE_TYPE_NONE = 0 ,   DMA_DONE_TYPE_DEFAULT = 1 ,   DMA_DONE_TYPE_AUTO_RESTART = 3 }
	DMA Done Types. More...

Detailed Description

Enumerated types for DMA driver.

Enumeration Type Documentation

dma_state_en

enum dma_state_en

DMA instance state indicators.

Enumerator
DMA_INSTANCE_INITIALIZED	DMA instance is initialized
DMA_INSTANCE_NOT_INITIALIZED	DMA instance is not initialized

dma_transfer_mode_en

enum dma_transfer_mode_en

DMA transfer modes.

Enumerator
DMA_TRANSFER_MODE_1D	1D transfer mode
DMA_TRANSFER_MODE_2D	2D transfer mode

dma_operation_type_en

enum dma_operation_type_en

DMA operation types (maps to hardware XTYPE/YTYPE fields)

Controls how data is handled when source and destination dimensions differ. Used for both X-direction (CH_CTRL.XTYPE) and Y-direction (CH_CTRL.YTYPE) operations.

Operation behavior:

• Source smaller than destination: Determines how to handle extra space
• Source larger than destination: Determines how to handle excess data
• Equal sizes: CONTINUE is most efficient

Examples (X-direction with src=100, dest=150):

• CONTINUE: Copy 100 elements, leave 50 undefined
• WRAP: Copy 100, then wrap and copy first 50 again
• FILL: Copy 100, then fill remaining 50 with FILLVAL
• DISABLE: No transfer (useful for Y-direction in 1D transfers)

Enumerator
DMA_OP_DISABLE	No data transfer (useful for 1D Y-direction)
DMA_OP_CONTINUE	Continuous copy (most common, best performance)
DMA_OP_WRAP	Wrap source data when destination is larger
DMA_OP_FILL	Fill remainder with FILLVAL when destination is larger

dma_security_en

enum dma_security_en

DMA security attributes.

Enumerator
DMA_SECURITY_SECURE	Secure access
DMA_SECURITY_NON_SECURE	Non-secure access

dma_privilege_en

enum dma_privilege_en

DMA privilege attributes.

Enumerator
DMA_PRIVILEGE_PRIVILEGED	Privileged access
DMA_PRIVILEGE_UNPRIVILEGED	Unprivileged access

dma_unit_size_en

enum dma_unit_size_en

DMA transfer unit sizes (maps to hardware TRANSIZE field)

Defines the size of each individual transfer unit. This sets the CH_SRCTRANSCFG.TRANSIZE and CH_DESTRANSCFG.TRANSIZE fields.

The total bytes per burst = unit_size × burst_size Example: DMA_UNIT_SIZE_4BYTES + DMA_BURST_SIZE_8 = 32 bytes per burst

Enumerator
DMA_UNIT_SIZE_1BYTE	1-byte per transfer unit
DMA_UNIT_SIZE_2BYTES	2-bytes per transfer unit
DMA_UNIT_SIZE_4BYTES	4-bytes per transfer unit
DMA_UNIT_SIZE_8BYTES	8-bytes per transfer unit
DMA_UNIT_SIZE_16BYTES	16-bytes per transfer unit

dma_burst_size_en

enum dma_burst_size_en

DMA burst lengths (maps to hardware MAXBURSTLEN field)

Defines how many transfer units are grouped together in a single burst before releasing the bus. This sets the CH_SRCTRANSCFG.MAXBURSTLEN and CH_DESTRANSCFG.MAXBURSTLEN fields.

Burst size affects:

• Bus efficiency (larger bursts = better efficiency)
• FIFO requirements (burst_size × transfer_size must fit in FIFO)
• Latency (larger bursts hold bus longer)

Example: DMA_BURST_SIZE_8 with DMA_TRANSFER_SIZE_4BYTES = 32 bytes per burst

Enumerator
DMA_BURST_SIZE_1	1 transfer unit per burst
DMA_BURST_SIZE_2	2 transfer units per burst
DMA_BURST_SIZE_4	4 transfer units per burst
DMA_BURST_SIZE_8	8 transfer units per burst
DMA_BURST_SIZE_16	16 transfer units per burst

dma_fifo_depth_en

enum dma_fifo_depth_en

DMA FIFO depths (extensible for future hardware)

Enumerator
DMA_FIFO_DEPTH_1	1 entry FIFO depth
DMA_FIFO_DEPTH_2	2 entries FIFO depth
DMA_FIFO_DEPTH_4	4 entries FIFO depth
DMA_FIFO_DEPTH_8	8 entries FIFO depth
DMA_FIFO_DEPTH_16	16 entries FIFO depth
DMA_FIFO_DEPTH_32	32 entries FIFO depth
DMA_FIFO_DEPTH_64	64 entries FIFO depth
DMA_FIFO_DEPTH_128	128 entries FIFO depth
DMA_CHANNEL_FIFO_DEPTH_ANY	Any FIFO depth

dma_reg_reload_type_en

enum dma_reg_reload_type_en

DMA register reload types (maps to hardware AUTOCFG register)

Defines how the DMA command reloads initial values at the end of a DMA cmd before autorestarting, ending, or linking to a new DMA command.

Register reload affects:

• Source/destination addresses (CH_SRCADDR/CH_DESADDR)
• Source/destination size registers (CH_XSIZE/CH_YSIZE)

Hardware behavior:

• Reloads happen before autorestart, command end, or linking
• When CLEARCMD is set, reloaded registers are also cleared
• Allows continuous operation without CPU intervention

Use cases:

• DISABLED: One-shot transfers, no reload
• SIZE_ONLY: Circular buffer (same addresses, reset sizes)
• SRC_ADDR_AND_SIZES: Reload source address + all sizes
• DEST_ADDR_AND_SIZES: Reload destination address + all sizes
• ALL_ADDR_AND_SIZES: Reload all addresses + all sizes

Enumerator
DMA_REG_RELOAD_DISABLED	000: Reload disabled
DMA_REG_RELOAD_SIZE_ONLY	001: Reload source and destination size registers only
DMA_REG_RELOAD_SRC_ADDR_AND_SIZES	011: Reload source address + all size registers
DMA_REG_RELOAD_DEST_ADDR_AND_SIZES	101: Reload destination address all size registers
DMA_REG_RELOAD_ALL_ADDR_AND_SIZES	111: Reload source/destination addresses all size registers

dma_trigger_target_en

enum dma_trigger_target_en

DMA trigger targets.

Enumerator
DMA_TRIGGER_SOURCE	Source trigger
DMA_TRIGGER_DEST	Destination trigger

dma_sw_trigger_type_en

enum dma_sw_trigger_type_en

DMA software trigger types (maps to hardware CMD register fields)

Controls the granularity and scope of software-triggered transfers. Used when manually triggering DMA transfers via software rather than hardware triggers or continuous operation.

Transfer hierarchy:

• Single: One transfer unit (size defined by TRANSIZE)
• Block: One complete X-dimension (XSIZE transfer units)

"Last" variants signal final transfer in a sequence:

• Useful for peripheral flow control
• Triggers completion processing
• May affect auto-restart behavior

Examples:

• SINGLE: Transfer 4 bytes (if TRANSIZE=4)
• BLOCK: Transfer complete line (XSIZE × TRANSIZE bytes)
• LAST_SINGLE: Final 4-byte transfer in sequence
• LAST_BLOCK: Final line transfer, trigger completion

Enumerator
DMA_SW_TRIG_SINGLE	Single transfer unit (TRANSIZE bytes)
DMA_SW_TRIG_LAST_SINGLE	Last single transfer unit (signals completion)
DMA_SW_TRIG_BLOCK	Complete X-dimension block (XSIZE units)
DMA_SW_TRIG_LAST_BLOCK	Last block transfer (signals end of operation)

dma_trigger_type_en

enum dma_trigger_type_en

DMA trigger types.

Enumerator
DMA_TRIG_SW_REQ	Single transfer unit (TRANSIZE bytes)
DMA_TRIG_RESERVED	Last single transfer unit (signals completion)
DMA_TRIG_HW_REQ	Complete X-dimension block (XSIZE units)
DMA_TRIG_INTERNAL_REQ	Last block transfer (signals end of operation)

dma_status_flags_en

enum dma_status_flags_en

DMA status flags (maps to hardware CH_STATUS register)

Enumerator
DMA_STATUS_DONE	Transfer done
DMA_STATUS_ERROR	Transfer error
DMA_STATUS_DISABLED	Channel disabled
DMA_STATUS_STOPPED	Channel stopped
DMA_STATUS_PAUSED	Channel paused
DMA_STATUS_BUSY	Channel busy/active
DMA_STATUS_WAITING	Channel waiting for trigger

dma_interrupt_flags_en

enum dma_interrupt_flags_en

DMA interrupt flags.

Enumerator
DMA_INT_DONE	Transfer done interrupt
DMA_INT_ERROR	Transfer error interrupt
DMA_INT_DISABLED	Channel disabled interrupt
DMA_INT_STOPPED	Channel stopped interrupt

dma_status_en

enum dma_status_en

DMA error codes.

Enumerator
DMA_OK	No error
DMA_ERROR_INVALID_INSTANCE	Invalid instance
DMA_ERROR_INVALID_CHANNEL	Invalid channel
DMA_ERROR_INVALID_CONFIG	Invalid configuration
DMA_ERROR_CHANNEL_BUSY	Channel is busy
DMA_ERROR_NO_CHANNELS	No channels available
DMA_ERROR_HARDWARE_ERROR	Hardware error
DMA_ERROR_INVALID_ADDRESS	Invalid memory address
DMA_ERROR_INVALID_SIZE	Invalid transfer size
DMA_ERROR_BURST_MISMATCH	Burst size larger than FIFO
DMA_ERROR_ALIGNMENT	Address alignment error
DMA_ERROR_TEMPLATE_NOT_SUPPORTED	Template not supported on this channel
DMA_ERROR_2D_NOT_SUPPORTED	2D transfer not supported on this channel
DMA_ERROR_TRIGGER_CONFLICT	Trigger port already in use
DMA_ERROR_INVALID_PARAMETER	Invalid input
DMA_ERROR_ALREADY_INITIALIZED	Already init
DMA_ERROR_NOT_INITIALIZED	Not initialized yet
DMA_ERROR_SEMAPHORE_ALLOC	Semaphore allocation
DMA_ERROR_MEMORY_ALLOC	Memory allocation
DMA_ERROR_TRANSFER_FAIL	Transfer Fail

dma_transfer_options_en

enum dma_transfer_options_en

DMA transfer options for simple API.

Enumerator
DMA_OPTION_NONE	Default options
DMA_OPTION_HIGH_PRIORITY	Use high priority
DMA_OPTION_SECURE	Use secure mode
DMA_OPTION_PRIVILEGED	Use privileged mode

dma_transfer_type_en

enum dma_transfer_type_en

DMA transfer types.

Enumerator
DMA_TRANSFER_TYPE_MEM2MEM	Memory to memory
DMA_TRANSFER_TYPE_PERIPH2MEM	Peripheral to memory
DMA_TRANSFER_TYPE_MEM2PERIPH	Memory to peripheral
DMA_TRANSFER_TYPE_STATIC	Static descriptor

dma_trigger_mode_en

enum dma_trigger_mode_en

DMA software trigger modes (maps to trigger mode field in hardware)

This controls how the software trigger interacts with the channel. Modes:

• COMMAND: Directly triggers a command
• FLOW: Used for flow control / pacing
• RESERVED: Reserved by hardware
• INTERNAL: Used for internal logic, not exposed normally

Enumerator
DMA_TRIG_MODE_COMMAND	Command mode: triggers transfer command
DMA_TRIG_MODE_RESERVED	Reserved: do not use
DMA_TRIG_MODE_FLOW	Flow mode: flow control or pacing
DMA_TRIG_MODE_INTERNAL	Internal: for internal HW use only

dma_donetype_en

enum dma_donetype_en

DMA Done Types.

Enumerator
DMA_DONE_TYPE_NONE	Done flag (STAT_DONE) won't be set
DMA_DONE_TYPE_DEFAULT	Default Done Type
DMA_DONE_TYPE_AUTO_RESTART	Done Type for auto restart mode