Functions for Clock Driver. More...

Functions
clk_status_en	clk_init_tree (clk_pll_config_en pll_config)
clk_status_en	clk_enable (clk_ids_en clk_id)
clk_status_en	clk_disable (clk_ids_en clk_id)
clk_status_en	clk_force_disable (clk_ids_en clk_id)
clk_status_en	clk_is_enabled (clk_ids_en clk_id, clk_enable_status_en *out_status)
clk_status_en	clk_get_rate (clk_ids_en clk_id, uint32_t *rate)
clk_status_en	clk_set_rate (clk_ids_en clk_id, uint32_t requested_rate, uint32_t *actual_rate)
clk_status_en	clk_get_divider (clk_ids_en clk_id, int32_t *divider)
clk_status_en	clk_set_pll_config (clk_pll_en pll, clk_pll_config_en pll_config)
clk_status_en	clk_get_pll_config (clk_pll_en pll, clk_pll_config_en *pll_config)
clk_status_en	clk_set_mux (clk_ids_en clk_id, uint8_t mux_out)

Detailed Description

Functions for Clock Driver.

Function Documentation

◆ clk_init_tree()

clk_status_en clk_init_tree ( clk_pll_config_en pll_config )

Initializes the clock tree with the specified PLL configuration.

Parameters

pll_config

PLL configuration to apply. Valid values:

CLK_PLL_CFG_OFF (0 MHz)
CLK_PLL_CFG_BYPASS (24 MHz)
CLK_PLL_CFG_LOW (100 MHz)
CLK_PLL_CFG_MID (200 MHz)
CLK_PLL_CFG_MID_PLUS (300 MHz)
CLK_PLL_CFG_HIGH (400 MHz)

Returns: CLK_OK if successful, otherwise CLK_ERROR_PARAMETER.

◆ clk_enable()

clk_status_en clk_enable ( clk_ids_en clk_id )

Enables the specified clock.

Parameters

clk_id Clock ID to enable.

Returns: CLK_OK if the clock was enabled successfully, otherwise error code.

◆ clk_disable()

clk_status_en clk_disable ( clk_ids_en clk_id )

Disables the specified clock.

Note: If any downstream clocks are enabled, this function will not disable the clock. Disable downstream clocks first or use clk_force_disable().

Parameters

clk_id Clock ID to disable.

Returns: CLK_OK if the clock was disabled successfully, otherwise error code.

◆ clk_force_disable()

clk_status_en clk_force_disable ( clk_ids_en clk_id )

Forcibly disables the specified clock regardless of downstream dependencies.

Parameters

clk_id Clock ID to forcibly disable.

Returns: CLK_OK if the clock was forcibly disabled, otherwise error code.

◆ clk_is_enabled()

clk_status_en clk_is_enabled	(	clk_ids_en	clk_id,
		clk_enable_status_en *	out_status )

Checks whether the specified clock is currently enabled.

Parameters

clk_id	Clock ID to check.
out_status	Pointer to store the clock enable status. Returns: CLK_STATUS_ENABLED CLK_STATUS_DISABLED

Returns: CLK_OK if the status was retrieved successfully, otherwise error code.

◆ clk_get_rate()

clk_status_en clk_get_rate	(	clk_ids_en	clk_id,
		uint32_t *	rate )

Retrieves the current operating frequency of the specified clock.

Parameters

clk_id	Clock ID.
rate	Pointer to store the current rate in Hz.

Returns: CLK_OK if the rate was retrieved successfully, otherwise error code.

◆ clk_set_rate()

clk_status_en clk_set_rate	(	clk_ids_en	clk_id,
		uint32_t	requested_rate,
		uint32_t *	actual_rate )

Sets the frequency of the specified clock. The behavior depends on the clock type:

If clk_id is CPU_CLK, valid rates are:
- CPU_CLK_RATE_HIGH (400 MHz)
- CPU_CLK_RATE_MID (200 MHz)
- CPU_CLK_RATE_LOW (100 MHz)
If clk_id is SYSPLL0_CLKOUT or SYSPLL1_CLKOUT, valid configurations are:
- CLK_PLL_CFG_OFF (0 MHz)
- CLK_PLL_CFG_BYPASS (24 MHz)
- CLK_PLL_CFG_LOW (100 MHz)
- CLK_PLL_CFG_MID (200 MHz)
- CLK_PLL_CFG_MID_PLUS (300 MHz)
- CLK_PLL_CFG_HIGH (400 MHz)
For other clocks, the closest supported frequency not exceeding the requested rate will be set based on divider configuration computed internally.

Parameters

clk_id	Clock ID to configure.
requested_rate	Desired frequency in Hz.
actual_rate	Pointer to store the actual configured rate in Hz.

Returns: CLK_OK if the rate was set successfully, otherwise error code.

◆ clk_get_divider()

clk_status_en clk_get_divider	(	clk_ids_en	clk_id,
		int32_t *	divider )

Retrieves the current divider value for the specified clock.

Parameters

clk_id	Clock ID.
divider	Pointer to store the current divider value.

Returns: CLK_OK if the divider was retrieved successfully, otherwise error code.

◆ clk_set_pll_config()

clk_status_en clk_set_pll_config	(	clk_pll_en	pll,
		clk_pll_config_en	pll_config )

Configures the specified PLL with a predefined frequency setup. This involves writing appropriate values to the PLL's reference divider, feedback divider, fractional divider, and post-dividers to achieve the target frequency. Special configurations like bypass and power-down modes are also supported.

Parameters

pll	Clock PLL to configure. Valid values: CLK_PLL0 CLK_PLL1
pll_config	PLL configuration to apply. Valid values: CLK_PLL_CFG_OFF (0 MHz) CLK_PLL_CFG_BYPASS (24 MHz) CLK_PLL_CFG_LOW (100 MHz) CLK_PLL_CFG_MID (200 MHz) CLK_PLL_CFG_MID_PLUS (300 MHz) CLK_PLL_CFG_HIGH (400 MHz)

Returns: CLK_OK if the configuration was applied successfully, otherwise error code.

◆ clk_get_pll_config()

clk_status_en clk_get_pll_config	(	clk_pll_en	pll,
		clk_pll_config_en *	pll_config )

Retrieves the current configuration of the specified PLL. This is done by reading the PLL's hardware divider settings - reference divider, feedback divider, fractional divider, and post-dividers and matching them against known PLL configuration presets. The function also detects if the PLL is operating in bypass mode or is powered down.

Parameters

pll	Clock PLL to query.
pll_config	Pointer to store the current PLL configuration.

Returns: CLK_OK if the configuration was retrieved successfully, otherwise error code.

◆ clk_set_mux()

clk_status_en clk_set_mux	(	clk_ids_en	clk_id,
		uint8_t	mux_out )

Sets the mux output configuration for the specified clock. This function configures the clock source selection (mux) for a given clock ID. It applies to clocks that support mux switching, such as PLL muxes or CGL clock muxes.

Parameters

clk_id	Clock ID for which the mux configuration is to be set.
mux_out	Desired mux output configuration. Valid values: 0 1

Returns: CLK_OK if the mux was set successfully, CLK_ERROR_PARAMETER if invalid parameters are passed, CLK_ERROR_INVALID_MUX if the clock does not support mux selection.