24#include "syna_device.h"
132#define CPU_CLK_RATE_HIGH 400000000
134#define CPU_CLK_RATE_MID 200000000
136#define CPU_CLK_RATE_LOW 100000000
clk_ids_en
Enumeration of all supported clock IDs in the system.
Definition sr110.h:594
clk_pll_en
PLL Identifiers.
Definition clk.h:155
clk_status_en
Status return values for clock APIs.
Definition clk.h:180
clk_enable_status_en
Clock enable status.
Definition clk.h:197
clk_pll_config_en
PLL configuration modes.
Definition clk.h:165
@ CLK_PLL1
Definition clk.h:157
@ CLK_PLL0
Definition clk.h:156
@ CLK_ERROR_UNSUPPORTED
Definition clk.h:185
@ CLK_ERROR_BUSY
Definition clk.h:183
@ CLK_ERROR_INVALID_MUX
Definition clk.h:187
@ CLK_ERROR
Definition clk.h:182
@ CLK_ERROR_TIMEOUT
Definition clk.h:184
@ CLK_ERROR_INVALID_VALUE
Definition clk.h:188
@ CLK_ERROR_CHILDREN_ENABLED
Definition clk.h:189
@ CLK_OK
Definition clk.h:181
@ CLK_ERROR_PARAMETER
Definition clk.h:186
@ CLK_STATUS_ENABLED
Definition clk.h:199
@ CLK_STATUS_DISABLED
Definition clk.h:198
@ CLK_PLL_CFG_MID
Definition clk.h:169
@ CLK_PLL_CFG_BYPASS
Definition clk.h:167
@ CLK_PLL_CFG_LOW
Definition clk.h:168
@ CLK_PLL_CFG_OFF
Definition clk.h:166
@ CLK_PLL_RATES_MAX
Definition clk.h:172
@ CLK_PLL_CFG_MID_PLUS
Definition clk.h:170
@ CLK_PLL_CFG_HIGH
Definition clk.h:171
clk_status_en clk_is_enabled(clk_ids_en clk_id, clk_enable_status_en *out_status)
clk_status_en clk_get_rate(clk_ids_en clk_id, uint32_t *rate)
clk_status_en clk_set_pll_config(clk_pll_en pll, clk_pll_config_en pll_config)
clk_status_en clk_set_rate(clk_ids_en clk_id, uint32_t requested_rate, uint32_t *actual_rate)
clk_status_en clk_get_divider(clk_ids_en clk_id, int32_t *divider)
clk_status_en clk_disable(clk_ids_en clk_id)
clk_status_en clk_enable(clk_ids_en clk_id)
clk_status_en clk_get_pll_config(clk_pll_en pll, clk_pll_config_en *pll_config)
clk_status_en clk_set_mux(clk_ids_en clk_id, uint8_t mux_out)
clk_status_en clk_init_tree(clk_pll_config_en pll_config)
clk_status_en clk_force_disable(clk_ids_en clk_id)