sr110_cm55.h

 
#ifndef SR110_CM55_H
#define SR110_CM55_H



typedef enum
{
    UART0     = 0,                    
    UART1     = 1,                    
    UARTLP    = 2,                    
    UART_COUNT                        
} uart_instance_en;



#define GPIO_0   0x1
#define GPIO_1   0x2
#define GPIO_2   0x4
#define GPIO_3   0x8
#define GPIO_4   0x10
#define GPIO_5   0x20
#define GPIO_6   0x40
#define GPIO_7   0x80
#define GPIO_8   0x100
#define GPIO_9   0x200
#define GPIO_10  0x400
#define GPIO_11  0x800
#define GPIO_12  0x1000
#define GPIO_13  0x2000
#define GPIO_14  0x4000
#define GPIO_15  0x8000
#define GPIO_16  0x10000
#define GPIO_17  0x20000
#define GPIO_18  0x40000
#define GPIO_19  0x80000
#define GPIO_20  0x100000
#define GPIO_21  0x200000
#define GPIO_22  0x400000
#define GPIO_23  0x800000
#define GPIO_24  0x1000000
#define GPIO_25  0x2000000
#define GPIO_26  0x4000000
#define GPIO_27  0x8000000
#define GPIO_28  0x10000000
#define GPIO_29  0x20000000
#define GPIO_30  0x40000000
#define GPIO_31  0x80000000
 
/* GPIO_PORT1 */
#define GPIO_32  0x1
#define GPIO_33  0x2
#define GPIO_34  0x4
#define GPIO_35  0x8
#define GPIO_36  0x10
#define GPIO_37  0x20
#define GPIO_38  0x40
#define GPIO_39  0x80
#define GPIO_40  0x100
#define GPIO_41  0x200
#define GPIO_42  0x400
#define GPIO_43  0x800
#define GPIO_44  0x1000
#define GPIO_45  0x2000
#define GPIO_46  0x4000
#define GPIO_47  0x8000



typedef enum {
    GPIO_PORT0   = 0,  
    GPIO_PORT1   = 1,  
    GPIO_LP_PORT = 2,  
    GPIO_COUNT         
} gpio_instance_en;




typedef enum {
    I2C_SLV_SDA         =  0,  
    I2C_SLV_SCL         =  1,  
    I3C_SLV_SDA         =  2,  
    I3C_SLV_SCL         =  3,  
    SPI_SLV_MISO        =  4,  
    SPI_SLV_CS          =  5,  
    SPI_SLV_MOSI        =  6,  
    SPI_SLV_CLK         =  7,  
    CIU_VSYNC           =  8,  
    GPIO9               =  9,  
    GPIO8               = 10,  
    GPIO5               = 11,  
    CIU_D3              = 12,  
    CIU_D6              = 13,  
    CIU_D7              = 14,  
    GPIO6               = 15,  
    GPIO7               = 16,  
    I2C0_MS_SDA         = 17,  
    I2C0_MS_SCL         = 18,  
    I2S_DI              = 19,  
    I2S_DO              = 20,  
    I2S_FSYNC           = 21,  
    I2S_BCLK            = 22,  
    SPI_MSTR_MOSI       = 23,  
    SPI_MSTR_CLK        = 24,  
    SPI_MSTR_CS         = 25,  
    SPI_MSTR_MISO       = 26,  
    SD0_CMD             = 27,  
    SD0_D0              = 28,  
    SD0_CLK             = 29,  
    SD0_D1              = 30,  
    SD0_D2              = 31,  
    SD0_D3              = 32,  
    JTAG_TMS            = 33,  
    JTAG_TCK            = 34,  
    SD1_CMD             = 35,  
    SD1_CLK             = 36,  
    SD1_D0              = 37,  
    SD1_D1              = 38,  
    SD1_D2              = 39,  
    SD1_D3              = 40,  
    RESET_N             = 41,  
    CLK32K_IN_PIN       = 42,  
    CLKOUT0             = 43,  
    CAMERA_MUTE         = 44,  
    AUDIO_MUTE          = 45,  
    I2C_PMU_SCL         = 46,  
    I2C_PMU_SDA         = 47,  
    SWIRE_CLK           = 48,  
    SWIRE_DATA          = 49,  
    PINMUX_BALL_NAME_LAST = 50 
} pinmux_pin_name_en;
 

typedef enum  {
    /* ********** External host pads ********** */
 
    /* pin-mux options for pad 17: I2C_SLV_SDA */
    I2C_SLV_SDA__GPIO44 = (I2C_SLV_SDA << PINMUX_FUNCTION_SHIFT) | 0x00,
    I2C_SLV_SDA__I2C_SLV_SDA = (I2C_SLV_SDA << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2C_SLV_SDA__UART0_TX = (I2C_SLV_SDA << PINMUX_FUNCTION_SHIFT) | 0x02,
 
    /* pin-mux options for pad 18: I2C_SLV_SCL */
    I2C_SLV_SCL__GPIO45 =(I2C_SLV_SCL << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2C_SLV_SCL__I2C_SLV_SCL = (I2C_SLV_SCL << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2C_SLV_SCL__UART0_RX = (I2C_SLV_SCL << PINMUX_FUNCTION_SHIFT) | 0x02,
 
     /* pin-mux options for pad 19: I3C_SLV_SDA */
    I3C_SLV_SDA__GPIO46 = (I3C_SLV_SDA << PINMUX_FUNCTION_SHIFT) | 0x00,
    I3C_SLV_SDA__I3C_SLV_SDA = (I3C_SLV_SDA << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* pin-mux options for pad 20: I3C_SLV_SCL */
    I3C_SLV_SCL__GPIO47 = (I3C_SLV_SCL << PINMUX_FUNCTION_SHIFT) | 0x00,
    I3C_SLV_SCL__I3C_SLV_SCL = (I3C_SLV_SCL << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* pin-mux options for pad 29: SPI_SLV_MISO */
    SPI_SLV_MISO__GPIO0 = (SPI_SLV_MISO << PINMUX_FUNCTION_SHIFT ) | 0x00,
    SPI_SLV_MISO__UART0_TX = (SPI_SLV_MISO << PINMUX_FUNCTION_SHIFT) | 0x01,
    SPI_SLV_MISO__SPI_SLV_MISO = (SPI_SLV_MISO << PINMUX_FUNCTION_SHIFT) | 0x02,
    SPI_SLV_MISO__LP_GPIO0 = (SPI_SLV_MISO << PINMUX_FUNCTION_SHIFT) | 0x03,
    SPI_SLV_MISO__AON_GPO0 = (SPI_SLV_MISO << PINMUX_FUNCTION_SHIFT) | 0x05,
 
    /* pin-mux options for pad 30: SPI_SLV_CS */
    SPI_SLV_CS__GPIO3 = (SPI_SLV_CS << PINMUX_FUNCTION_SHIFT) | 0x00,
    SPI_SLV_CS__SPI_SLV_CS = (SPI_SLV_CS << PINMUX_FUNCTION_SHIFT) | 0x01,
    SPI_SLV_CS__UART_LP_RX = (SPI_SLV_CS << PINMUX_FUNCTION_SHIFT) | 0x02,
    SPI_SLV_CS__SD0_WP = (SPI_SLV_CS << PINMUX_FUNCTION_SHIFT) | 0x03,
    SPI_SLV_CS__LP_GPIO3 = (SPI_SLV_CS << PINMUX_FUNCTION_SHIFT) | 0x04,
    SPI_SLV_CS__AON_GPI1 = (SPI_SLV_CS << PINMUX_FUNCTION_SHIFT) | 0x05,
 
     /* pin-mux options for pad 31: SPI_SLV_MOSI */
    SPI_SLV_MOSI__GPIO1 = (SPI_SLV_MOSI << PINMUX_FUNCTION_SHIFT) | 0x00,
    SPI_SLV_MOSI__UART0_RX = (SPI_SLV_MOSI << PINMUX_FUNCTION_SHIFT) |0x01,
    SPI_SLV_MOSI__SPI_SLV_MOSI = (SPI_SLV_MOSI << PINMUX_FUNCTION_SHIFT) | 0x02,
    SPI_SLV_MOSI__LP_GPIO1 = (SPI_SLV_MOSI << PINMUX_FUNCTION_SHIFT) | 0x03,
    SPI_SLV_MOSI__AON_GPI0 = (SPI_SLV_MOSI << PINMUX_FUNCTION_SHIFT) |0x05,
 
     /* pin-mux options for pad 32: SPI_SLV_CLK */
    SPI_SLV_CLK__GPIO2 = (SPI_SLV_CLK << PINMUX_FUNCTION_SHIFT) | 0x00,
    SPI_SLV_CLK__SPI_SLV_CLK = (SPI_SLV_CLK << PINMUX_FUNCTION_SHIFT) | 0x01,
    SPI_SLV_CLK__UART_LP_TX = (SPI_SLV_CLK << PINMUX_FUNCTION_SHIFT) | 0x02,
    SPI_SLV_CLK__SD0_CDn = (SPI_SLV_CLK << PINMUX_FUNCTION_SHIFT) | 0x03,
    SPI_SLV_CLK__LP_GPIO2 = (SPI_SLV_CLK << PINMUX_FUNCTION_SHIFT) | 0x04,
    SPI_SLV_CLK__AON_GPO1 = (SPI_SLV_CLK << PINMUX_FUNCTION_SHIFT) | 0x05,
 
    /* ********** LP I/O Camera pads ********** */
 
    /* pin-mux options for pad 38: CIU_VSYNC */
    CIU_VSYNC__GPIO4 = (CIU_VSYNC << PINMUX_FUNCTION_SHIFT) | 0x00,
    CIU_VSYNC__CIU_VSYNC = (CIU_VSYNC << PINMUX_FUNCTION_SHIFT) | 0x01,
    CIU_VSYNC__UART0_CTS = (CIU_VSYNC << PINMUX_FUNCTION_SHIFT) | 0x03,
    CIU_VSYNC__AON_GPI3 = (CIU_VSYNC << PINMUX_FUNCTION_SHIFT) |0x05,
 
    /* pin-mux options for pad 39: GPIO9 */
    GPIO9__JTAG_TDO = (GPIO9 << PINMUX_FUNCTION_SHIFT) | 0x00,
    GPIO9__CIU_D2 = (GPIO9 << PINMUX_FUNCTION_SHIFT) | 0x01,
    GPIO9__GPIO9 = (GPIO9 << PINMUX_FUNCTION_SHIFT) | 0x02,
    GPIO9__SPI_SLV_MISO = (GPIO9 << PINMUX_FUNCTION_SHIFT)| 0x03,
    GPIO9__AON_CAMERA_TRIGGER = (GPIO9 << PINMUX_FUNCTION_SHIFT)| 5,
 
    /* pin-mux options for pad 40: GPIO8 */
    GPIO8__JTAG_TDI = (GPIO8 << PINMUX_FUNCTION_SHIFT) | 0x00,
    GPIO8__CIU_D1 =  (GPIO8 << PINMUX_FUNCTION_SHIFT) | 0x01,
    GPIO8__GPIO8 = (GPIO8 << PINMUX_FUNCTION_SHIFT) | 0x02,
    GPIO8__SPI_SLV_CS = (GPIO8 << PINMUX_FUNCTION_SHIFT) | 0x03,
    GPIO8__AON_GPO2 = (GPIO8 << PINMUX_FUNCTION_SHIFT) | 0x05,
 
    /* pin-mux options for pad 41: GPIO5 */
    GPIO5__JTAG_TRSTN = (GPIO5 << PINMUX_FUNCTION_SHIFT) | 0x00,
    GPIO5__CIU_HSYNC = (GPIO5 << PINMUX_FUNCTION_SHIFT) | 0x01,
    GPIO5__GPIO5 = (GPIO5 <<PINMUX_FUNCTION_SHIFT) | 0x02,
    GPIO5__UART0_RTS = (GPIO5 << PINMUX_FUNCTION_SHIFT) | 0x3,
    GPIO5__AON_GPI2 = (GPIO5 << PINMUX_FUNCTION_SHIFT) | 0x05,
 
    /* pin-mux options for pad 42: CIU_D3 */
    CIU_D3__GPIO10 = (CIU_D3 << PINMUX_FUNCTION_SHIFT) | 0x00,
    CIU_D3__CIU_D3 = (CIU_D3 << PINMUX_FUNCTION_SHIFT) | 0x01,
    CIU_D3__CLKOUT1 = (CIU_D3 << PINMUX_FUNCTION_SHIFT) | 0x02,
    CIU_D3__DM0_CLK = (CIU_D3 << PINMUX_FUNCTION_SHIFT) | 0x03,
    CIU_D3__AON_CLKOUT1 = (CIU_D3 << PINMUX_FUNCTION_SHIFT) | 0x05,
 
    /* pin-mux options for pad 90: CIU_D6 */
    CIU_D6__GPIO13 = (CIU_D6 << PINMUX_FUNCTION_SHIFT) | 0x00,
    CIU_D6__CIU_D6 = (CIU_D6 << PINMUX_FUNCTION_SHIFT) | 0x01,
    CIU_D6__DM0_CLK = (CIU_D6 << PINMUX_FUNCTION_SHIFT) | 0x02,
    CIU_D6__UART1_TX = (CIU_D6 << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 91: CIU_D7 */
    CIU_D7__GPIO14 = (CIU_D7 << PINMUX_FUNCTION_SHIFT) | 0x00,
    CIU_D7__CIU_D7 = (CIU_D7 << PINMUX_FUNCTION_SHIFT) | 0x01,
    CIU_D7__DM0_DATA = (CIU_D7 << PINMUX_FUNCTION_SHIFT) | 0x02,
    CIU_D7__UART1_RX = (CIU_D7 << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 102: GPIO6 */
    GPIO6__GPIO6 = (GPIO6 << PINMUX_FUNCTION_SHIFT) | 0x00,
    GPIO6__CIU_BCLK = (GPIO6 << PINMUX_FUNCTION_SHIFT) | 0x01,
    GPIO6__SPI_DVI_CLK = (GPIO6 << PINMUX_FUNCTION_SHIFT) | 0x02,
    GPIO6__SPI_SLV_CLK = (GPIO6 << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 103: GPIO7 */
    GPIO7__GPIO7 = (GPIO7 << PINMUX_FUNCTION_SHIFT) | 0x00,
    GPIO7__CIU_D0 = (GPIO7 << PINMUX_FUNCTION_SHIFT) | 0x01,
    GPIO7__SPI_DVI_SI = (GPIO7 << PINMUX_FUNCTION_SHIFT) | 0x02,
    GPIO7__SPI_SLV_MOSI = (GPIO7 << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* ********** Sensor control ********** */
 
    /* pin-mux options for pad 88: I2C0_MS_SDA */
    I2C0_MS_SDA__GPIO16 = (I2C0_MS_SDA << PINMUX_FUNCTION_SHIFT) | 0x00,
    I2C0_MS_SDA__I2C0_MS_SDA = (I2C0_MS_SDA << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2C0_MS_SDA__I3C_MS_SDA = (I2C0_MS_SDA << PINMUX_FUNCTION_SHIFT) | 0x02,
    I2C0_MS_SDA__DM0_DATA = (I2C0_MS_SDA << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 89: I2C0_MS_SCL */
    I2C0_MS_SCL__GPIO15 = (I2C0_MS_SCL << PINMUX_FUNCTION_SHIFT) | 0x00,
    I2C0_MS_SCL__I2C0_MS_SCL = (I2C0_MS_SCL << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2C0_MS_SCL__I3C_MS_SCL = (I2C0_MS_SCL<< PINMUX_FUNCTION_SHIFT) | 0x02,
    I2C0_MS_SCL__DM0_CLK = (I2C0_MS_SCL << PINMUX_FUNCTION_SHIFT ) | 0x03,
 
    /* ********** I2S/SoundWire ********** */
 
    /* pin-mux options for pad 186: I2S_DI */
    I2S_DI__GPIO20 = (I2S_DI << PINMUX_FUNCTION_SHIFT) | 0x00,
    I2S_DI__I2S_DI = (I2S_DI << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2S_DI__TRACE_DATA0 = (I2S_DI << PINMUX_FUNCTION_SHIFT) | 0x02,
    I2S_DI__DM1_DATA = (I2S_DI << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 187: I2S_DO */
    I2S_DO__GPIO19 = (I2S_DO << PINMUX_FUNCTION_SHIFT) | 0x00,
    I2S_DO__I2S_DO = (I2S_DO << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2S_DO__TRACE_DATA1 = (I2S_DO << PINMUX_FUNCTION_SHIFT) | 0x02,
    I2S_DO__DM1_CLK = (I2S_DO << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 188: I2S_FSYNC */
    I2S_FSYNC__GPIO18 = (I2S_FSYNC << PINMUX_FUNCTION_SHIFT) | 0x00,
    I2S_FSYNC__I2S_FSYNC = (I2S_FSYNC << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2S_FSYNC__TRACE_DATA2 = (I2S_FSYNC << PINMUX_FUNCTION_SHIFT) | 0x02,
    I2S_FSYNC__DM_HOST_DATA = (I2S_FSYNC << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 189: I2S_BCLK */
    I2S_BCLK__GPIO17 = (I2S_BCLK << PINMUX_FUNCTION_SHIFT) | 0x00,
    I2S_BCLK__I2S_BCLK = (I2S_BCLK << PINMUX_FUNCTION_SHIFT) | 0x01,
    I2S_BCLK__TRACE_DATA3 = (I2S_BCLK << PINMUX_FUNCTION_SHIFT) | 0x02,
    I2S_BCLK__DM_HOST_CLK = (I2S_BCLK << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* ********** SPI Master ********** */
 
    /* pin-mux options for pad 92: SPI_MSTR_MOSI */
    SPI_MSTR_MOSI__GPIO23 = (SPI_MSTR_MOSI << PINMUX_FUNCTION_SHIFT) | 0x00,
    SPI_MSTR_MOSI__SPI_MSTR_MOSI = (SPI_MSTR_MOSI << PINMUX_FUNCTION_SHIFT) | 0x01,
    SPI_MSTR_MOSI__UART1_TX = (SPI_MSTR_MOSI << PINMUX_FUNCTION_SHIFT) | 0x02,
    SPI_MSTR_MOSI__I2C1_MS_SCL = (SPI_MSTR_MOSI << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 93: SPI_MSTR_CLK */
    SPI_MSTR_CLK__GPIO22 = (SPI_MSTR_CLK << PINMUX_FUNCTION_SHIFT) | 0x00,
    SPI_MSTR_CLK__SPI_MSTR_CLK = (SPI_MSTR_CLK << PINMUX_FUNCTION_SHIFT) | 0x01,
    SPI_MSTR_CLK__UART0_RX = (SPI_MSTR_CLK << PINMUX_FUNCTION_SHIFT) | 0x02,
    SPI_MSTR_CLK__CIU_D5 = (SPI_MSTR_CLK << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 98: SPI_MSTR_CS */
    SPI_MSTR_CS__GPIO21 = (SPI_MSTR_CS << PINMUX_FUNCTION_SHIFT) | 0x00,
    SPI_MSTR_CS__SPI_MSTR_CS = (SPI_MSTR_CS << PINMUX_FUNCTION_SHIFT) | 0x01,
    SPI_MSTR_CS__UART0_TX = (SPI_MSTR_CS <<PINMUX_FUNCTION_SHIFT) | 0x02,
    SPI_MSTR_CS__CIU_D4 = (SPI_MSTR_CS << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* pin-mux options for pad 99: SPI_MSTR_MISO */
    SPI_MSTR_MISO__GPIO24 = (SPI_MSTR_MISO << PINMUX_FUNCTION_SHIFT) | 0x00,
    SPI_MSTR_MISO__SPI_MSTR_MISO = (SPI_MSTR_MISO << PINMUX_FUNCTION_SHIFT) | 0x01,
    SPI_MSTR_MISO__UART1_RX = (SPI_MSTR_MISO << PINMUX_FUNCTION_SHIFT) | 0x02,
    SPI_MSTR_MISO__I2C1_MS_SDA = (SPI_MSTR_MISO << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* ********** SD Card ********** */
 
    /* pin-mux options for pad 78: SD0_CMD */
    SD0_CMD__GPIO25 = (SD0_CMD << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD0_CMD__SD0_CMD = (SD0_CMD << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* pin-mux options for pad 79: SD0_D0 */
    SD0_D0__GPIO27 = (SD0_D0 << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD0_D0__SD0_D0 = (SD0_D0 << PINMUX_FUNCTION_SHIFT) | 0x01,
    SD0_D0__DM0_DATA = (SD0_D0 << PINMUX_FUNCTION_SHIFT) | 0x02,
    SD0_D0__CALIB_DLY_PWM = (SD0_D0 << PINMUX_FUNCTION_SHIFT) | 0x04,
    SD0_D0__UART_LP_RX = (SD0_D0 << PINMUX_FUNCTION_SHIFT) | 0x05,
 
    /* pin-mux options for pad 80: SD0_CLK */
    SD0_CLK__GPIO26 = (SD0_CLK << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD0_CLK__SD0_CLK = (SD0_CLK << PINMUX_FUNCTION_SHIFT) | 0x01,
    SD0_CLK__DM0_CLK = (SD0_CLK << PINMUX_FUNCTION_SHIFT) | 0x02,
    SD0_CLK__TRACE_CLK = (SD0_CLK << PINMUX_FUNCTION_SHIFT) | 0x03,
    SD0_CLK__CALIB_DLY_OUT = (SD0_CLK << PINMUX_FUNCTION_SHIFT) | 0x04,
    SD0_CLK__UART_LP_TX = (SD0_CLK << PINMUX_FUNCTION_SHIFT) | 0x05,
 
    /* pin-mux options for pad 81: SD0_D1 */
    SD0_D1__GPIO28 = (SD0_D1 << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD0_D1__SD0_D1 = (SD0_D1 << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* pin-mux options for pad 82: SD0_D2 */
    SD0_D2__GPIO29 = (SD0_D2 << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD0_D2__SD0_D2 = (SD0_D2 << PINMUX_FUNCTION_SHIFT) | 0x01,
    SD0_D2__DM1_CLK = (SD0_D2 << PINMUX_FUNCTION_SHIFT)| 0x02,
 
    /* pin-mux options for pad 83: SD0_D3 */
    SD0_D3__GPIO30 = (SD0_D3 << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD0_D3__SD0_D3 = (SD0_D3 << PINMUX_FUNCTION_SHIFT) | 0x01,
    SD0_D3__DM1_DATA = (SD0_D3 << PINMUX_FUNCTION_SHIFT) | 0x02,
 
    /* ********** JTAG SWD ********** */
 
    /* pin-mux options for pad 100: JTAG_TMS */
    JTAG_TMS__JTAG_TMS = (JTAG_TMS << PINMUX_FUNCTION_SHIFT) | 0x00,
    JTAG_TMS__GPIO32 = (JTAG_TMS << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* pin-mux options for pad 101: JTAG_TCK */
    JTAG_TCK__JTAG_TCK = (JTAG_TCK << PINMUX_FUNCTION_SHIFT) | 0x00,
    JTAG_TCK__GPIO31 = (JTAG_TCK << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* ********** SD WIFI ********** */
 
    /* pin-mux options for pad 172: SD1_CMD */
    SD1_CMD__GPIO34 = (SD1_CMD << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD1_CMD__SD1_CMD = (SD1_CMD << PINMUX_FUNCTION_SHIFT) | 0x01,
    SD1_CMD__JTAG_TRSTN = (SD1_CMD << PINMUX_FUNCTION_SHIFT) | 0x02,
 
    /* pin-mux options for pad 173: SD1_CLK */
    SD1_CLK__GPIO35 = (SD1_CLK << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD1_CLK__SD1_CLK = (SD1_CLK << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* pin-mux options for pad 174: SD1_D0 */
    SD1_D0__GPIO36 = (SD1_D0 << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD1_D0__SD1_D0 = (SD1_D0 << PINMUX_FUNCTION_SHIFT) | 0x01,
    SD1_D0__JTAG_TDI = (SD1_D0 << PINMUX_FUNCTION_SHIFT) | 0x02,
 
    /* pin-mux options for pad 175: SD1_D1 */
    SD1_D1__GPIO37 = (SD1_D1 << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD1_D1__SD1_D1 = (SD1_D1 << PINMUX_FUNCTION_SHIFT) | 0x01,
    SD1_D1__JTAG_TDO = (SD1_D1 << PINMUX_FUNCTION_SHIFT) | 0x02,
 
    /* pin-mux options for pad 184: SD1_D2 */
    SD1_D2__GPIO38 = (SD1_D2 << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD1_D2__SD1_D2 = (SD1_D2 << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* pin-mux options for pad 185: SD1_D3 */
    SD1_D3__GPIO39 = (SD1_D3 << PINMUX_FUNCTION_SHIFT) | 0x00,
    SD1_D3__SD1_D3 = (SD1_D3 << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* ********** SPECIAL PINS ********** */
 
    /* pin-mux options for pad 33: RESET_N */
    RESET_N__RESET_N = (RESET_N << PINMUX_FUNCTION_SHIFT) |0x00,
 
    /* pin-mux options for pad 43: CLK32K_IN */
    CLK32K_IN_PIN__GPIO40 = (CLK32K_IN_PIN << PINMUX_FUNCTION_SHIFT) | 0x00,
    CLK32K_IN_PIN__CLK32K_IN = (CLK32K_IN_PIN << PINMUX_FUNCTION_SHIFT) | 0x01,
 
    /* pin-mux options for pad 44: CLKOUT0 */
    CLKOUT0__GPIO41 = (CLKOUT0 << PINMUX_FUNCTION_SHIFT) | 0x00,
    CLKOUT0__CLKOUT0 = (CLKOUT0 << PINMUX_FUNCTION_SHIFT) | 0x01,
    CLKOUT0__AON_CAMERA_CLK = (CLKOUT0 << PINMUX_FUNCTION_SHIFT) | 0x05,
 
    /* pin-mux options for pad 170: CAMERA_MUTE */
    CAMERA_MUTE__CAMERA_MUTE = (CAMERA_MUTE << PINMUX_FUNCTION_SHIFT) | 0x00,
 
    /* pin-mux options for pad 171: AUDIO_MUTE */
    AUDIO_MUTE__AUDIO_MUTE = (AUDIO_MUTE << PINMUX_FUNCTION_SHIFT) | 0x00,
 
    /* ********** SWIRE ********** */
 
    /* pin-mux options for pad 197: SWIRE_CLK */
    SWIRE_CLK__GPIO42 = (SWIRE_CLK << PINMUX_FUNCTION_SHIFT) | 0x00,
    SWIRE_CLK__I2C1_MS_SCL = (SWIRE_CLK << PINMUX_FUNCTION_SHIFT) | 0x03,
 
 
    /* pin-mux options for pad 198: SWIRE_DATA */
    SWIRE_DATA__GPIO43 = (SWIRE_DATA << PINMUX_FUNCTION_SHIFT) | 0x00,
    SWIRE_DATA__I2C1_MS_SDA = (SWIRE_DATA << PINMUX_FUNCTION_SHIFT) | 0x03,
 
    /* ********** AON I2C ********** */
 
    /* pin-mux options for pad 25: I2C_PMU_SCL */
    I2C_PMU_SCL__I2C_PMU_SCL = (I2C_PMU_SCL << PINMUX_FUNCTION_SHIFT) | 0x00,
 
    /* pin-mux options for pad 26: I2C_PMU_SDA */
    I2C_PMU_SDA__I2C_PMU_SDA = (I2C_PMU_SDA << PINMUX_FUNCTION_SHIFT) | 0x00,
 
    /* Max num of pin functions */
    MAX_NUM_OF_PIN_FUNCTIONS = 7
} pinmux_functions_en;
 




typedef enum {
    SPI_C = 0,              
    SPI_P,                  
    SPI_INSTANCE_COUNT      
} spi_instance_en;

typedef enum {
    CONTROLLER = 1,         
    PERIPHERAL = 0          
} spi_mode_en;




typedef enum
{
    I2CM0 = 0,           
    I2CM1,               
    I2CS,                
    I2C_INSTANCE_COUNT   
} i2c_instance_en;




typedef enum 
{
    NULL_CLK,               
    XTAL_PAD_CLK,           
    HP_RC,                  
    LP_RC,                  
    CLK32K_IN,              
    SYSPLL0_CLKOUT,         
    SYSPLL1_CLKOUT,         
 
    /* System Clocks */
    SOC_BASE_CLK,           
    BCM_CLK,                
    AHB_CLK,                
    APB_CLK,                
 
    /* CPU Sub System Clocks */
    CPU_CLK,                
    NPU_CLK,                
    AXI_CLK,                
    CPU_CNT_CLK,            
    DMA0_CLK,               
    DMA1_CLK,               
 
    /* Calibration */
    CALIB_CLK,              
 
    /* PVT */
    PVT_HS_CLK,             
    PVT_APB_CLK,            
 
    /* Image Processing Clocks */
    IPI_CLK,                
    IMG_CFG_CLK,            
    IMG_APB_CLK,            
    IMG_SYS_CLK,            
    IMG_RES_CLK,            
    IMG_CAM_CLK,            
    IMG_DPHY_CFG_CLK,       
    IMG_DPHYRX1_TXCLKESC,   
    IMG_DPHYRX2_TXCLKESC,   
    IMG_SCAN_BYTE_CLK,      
    IMG_TEST_CLK150M_GRP0,  
    IMG_TEST_CLK312P5M_GRP0,
    IMG_TEST_CLK312P5M_GRP1,
    IMG_TEST_CLK400M_GRP0,  
 
    /* Peripheral Clocks */
    SPI_MSTR_CFG_CLK,       
    SPI_MSTR_SSI_CLK,       
    SPI_SLV_CFG_CLK,        
    SPI_SLV_SSI_CLK,        
    I3C0_CFG_CLK,           
    I3C0_CORE_CLK,          
    I3C1_CFG_CLK,           
    I3C1_CORE_CLK,          
    UART0_CFG_CLK,          
    UART0_CORE_CLK,         
    UART1_CFG_CLK,          
    UART1_CORE_CLK,         
    I2C0_MSTR_CFG_CLK,      
    I2C0_MSTR_CORE_CLK,     
    I2C1_MSTR_CFG_CLK,      
    I2C1_MSTR_CORE_CLK,     
    I2C_SLV_CFG_CLK,        
    I2C_SLV_CORE_CLK,       
    SWIRE_CFG_CLK,          
    GPIO_CFG_CLK,           
    GPIO_DB_CLK,            
 
    /* I2S */
    I2S_CFG_CLK,            
    I2S_TX0_PCLK,           
    I2S_TX1_PCLK,           
    I2S_TX2_PCLK,           
    I2S_TX3_PCLK,           
    I2S_RX0_PCLK,           
    I2S_RX1_PCLK,           
    I2S_RX2_PCLK,           
    I2S_RX3_PCLK,           
    I2S_MSTR_BCLK,          
 
    /* XSPI */
    XSPI_CFG_CLK,           
    XSPI_CORE_CLK,          
    XSPI_AXI_CLK,           
 
    /* SDIO 0 */
    SD0_CORE_CLK,           
    SD0_AXI_CLK,            
    SD0_CFG_CLK,            
 
    /* SDIO 1 */
    SD1_CORE_CLK,           
    SD1_AXI_CLK,            
    SD1_CFG_CLK,            
 
    /* USB2.0 OTG */
    USB2_CORE_CLK,          
    USB2_AXI_CLK,           
    USB2_REF_CLK,           
    USB2_CFG_CLK,           
    USB2_TEST_CLK,          
    PERIF_TEST_CLK480M_GRP0,
    PERIF_TEST_CLK480M_GRP1,
    PERIF_TEST_CLK480M_GRP2,
    PERIF_TEST_CLK100M_GRP0,
    PERIF_TEST_CLK100M_GRP1,
    PERIF_TEST_CLK100M_GRP2,
    PERIF_TEST_CLK100M_GRP3,
    PERIF_TEST_CLK100M_GRP4,
 
    /* LP Processor Clocks */
    LPP_HCLK,               
    LPP_MEMA_CLK,           
    LPP_MEMB_CLK,           
    LPP_M4CACHE_CLK,        
    LPP_M4_HCLK,            
    LPP_M4_FCLK,            
    LPP_M4_DAP_CLK,         
    LPP_M4_CTI_CLK,         
    LPP_LX7_CLK,            
    LPP_LX7_PCLK,           
    LPP_NNMSS_CLK,          
    LPP_NNENG_CLK,          
    LPP_APB_CLK,            
    LPP_CFG_PCLK,           
    LPP_WDOG_PCLK,          
    LPP_TIMER1_PCLK,        
    LPP_TIMER2_PCLK,        
    LPP_TIMER1_CLK,         
    LPP_TIMER2_CLK,         
    LPP_WDOG_CLK,           
    LPP_GPIO_DB_CLK,        
    LPP_UART_PCLK,          
    LPP_GPIO_PCLK,          
    LPP_GPIO_PCLK_INT,      
    LPP_UART_SCLK,          
 
    /* LP Sense Clocks */
    LP_BASE_CLK,            
    LP_BASE_CLK_GATE,       
    GEAR2_BASE_CLK,         
    LPS_MEM_CLK,            
    LPS_IMG_CLK,            
    LPS_CORE_CLK,           
    LPS_JPEG_CLK,           
    LPS_CSI_AHB_CLK,        
    LPS_REG_CLK,            
    LPS_IMGSENSE_CLK,       
    LPS_AUDSENSE_CLK,       
    LPS_IMGIFC_CLK,         
    LPS_JPEG_WRAP_CLK,      
    LPS_STS_MEM_CLK,        
    LPS_DDF0_CLK,           
    LPS_DDF1_CLK,           
    LPS_DDF2_CLK,           
    LPS_DDF3_CLK,           
    LPS_HW_VAD_CLK,         
    LPS_IPI_CLK,            
    AUDIO_CLK,              
    LPS_DM_CLK,             
    I2S_CORE_CLK,           
    GEAR3_BASE_CLK,         
    GEAR3_AUX_CLK,          
    LPS_RES_CLK,            
    CFG_CLK,                
    AON_BASE_CLK,           
    AON_SLEEP_CLK,          
 
    MAX_CLOCKS_CLK          
} clk_ids_en;

typedef enum
{
    CLK_PLL_CFG_OFF,     
    CLK_PLL_CFG_BYPASS,       
    CLK_PLL_CFG_LOW,     
    CLK_PLL_CFG_MID,     
    CLK_PLL_CFG_MID_PLUS,   
    CLK_PLL_CFG_HIGH,       
    CLK_PLL_RATES_MAX      
} clk_pll_config_en;

typedef enum
{
    CLK_STATUS_DISABLED,       
    CLK_STATUS_ENABLED           
} clk_enable_status_en;

typedef enum
{
    CLK_PLL0,   
    CLK_PLL1    
} clk_pll_en;

typedef enum 
{  
    OSC,          
    PLL,          
    GATE,         
    CGL,          
    I2S_CTRL      
} clk_type_en;




typedef enum dma_instance
{
    DMA_0 = 0,                   
    DMA_1 = 1,                   
    DMA_INSTANCE_COUNT           
} dma_instance_en;




typedef enum
{
    SDIO0     = 0,               
    SDIO1     = 1,               
    SDIO_COUNT                   
} sdio_instance_en;




typedef enum {
    XSPI_INSTANCE_0 = 0,         
    XSPI_INSTANCE_COUNT          
} xspi_instance_en;

 
#endif // SR110_CM55_H