Data Structures

Here are the data structures with brief descriptions:

Ccan_config_t	Runtime CAN controller configuration
Ccan_hw_config_t	Hardware-specific CAN controller configuration
Ccan_rx_classic_header_t	Header layout reported for a received Classical CAN frame
Ccan_rx_fd_header_t	Header layout reported for a received CAN FD frame
Ccan_rx_filter_t	Receive filter entry matched against incoming CAN identifiers
Ccan_rx_frame_t	Receive frame container returned to RX callbacks
Ccan_tx_frame_t	Transmit frame layout written into CAN hardware memory
Ccan_tx_schedule_time_t	64-bit timestamp used for scheduled transmit requests
Cdata_buffer_thld_t	Threshold configuration for I³C data buffers. Supported values in dwords are 1, 4, 8, 16, 32, 64
Cdma_1d_config_t	DMA 1D transfer configuration
Cdma_2d_config_t	DMA 2D transfer configuration
Cdma_auto_restart_config_t	DMA auto-restart configuration
Cdma_channel_attr_t	DMA channel request configuration and capabilities
Cdma_channel_config_t	DMA channel configuration
Cdma_hw_trigger_config_t	DMA hardware trigger configuration
Cdma_sw_trigger_config_t	DMA software trigger configuration
Cdma_template_config_t	DMA template configuration (used with 1D transfers only)
Cdmic_buffer_context_s	DMIC buffer context structure
Cdmic_capability_s	DMIC instance capability description
Cdmic_channel_config_s	DMIC channel configuration structure
Cdmic_data_path_config_s	Unified DMIC data-path configuration
Cdmic_dma_config_s	Generic DMA configuration
Cdmic_fifo_config_s	DMIC RX FIFO configuration structure
Cdmic_io_config_s	DMIC I/O configuration structure
Cgpio_pin_config_t	Configuration for a single GPIO pin
Ci2c_blocking_config_t	Blocking transfer configuration
Ci2c_controller_config_t	I²C controller configuration structure
Ci2c_nonblocking_config_t	Non-blocking transfer configuration
Ci2c_target_config_t	I²C target configuration structure
Ci2s_capabilities_t	I2S capabilities structure
Ci2s_clock_mode_t	I2S clock configuration structure
Ci2s_config_t	I2S configuration structure
Ci2s_mem_if_ops_t	I2S memory interface operations
Ci3c_bus_avail_timing_t	Bus availability timing configuration
Ci3c_ccc_response_entry_t	One CCC response queue entry
Ci3c_controller_config_t	I³C controller configuration structure
Ci3c_controller_policy_config_t	Controller behavior policy independent from hardware timing/setup
Ci3c_current_xfer_t	Information about the current I³C transfer
Ci3c_dat_entry_t	Logical DAT entry view exposed by API
Ci3c_device_config_t	Abstracted I³C device configuration structure
Ci3c_device_t	Persistent descriptor for an I³C/I²C target device
Ci3c_event_info_t	Structured I³C callback event information
Ci3c_hdr_config_t	HDR mode configuration
Ci3c_ibi_config_t	IBI (In-Band Interrupt) configuration
Ci3c_interrupt_config_t	Notification and interrupt policy for controller mode
Ci3c_scl_timing_t	Complete SCL timing configuration for I³C
Ci3c_sir_config_t	SIR (Target-Initiated Request) configuration
Ci3c_target_config_t	I³C target mode configuration structure. Contains timing, addressing, and operational parameters for target device initialization
Ci3c_target_id_t	BCR, DCR, PID details of the i3c target
Ci3c_threshold_ctrl_t	Combined threshold configuration for I³C
Ci3c_transfer_t	Unified transfer descriptor
Cpinmux_config_all_t	Combined configuration for electrical parameters and function routing
Cpinmux_elec_config_t	Electrical characteristics configuration for a pin
Cqueue_thld_t	Threshold configuration for I³C queues
Cscl_ext_low_count_timing_t	Extended low count timing configuration
Cscl_fast_mode_plus_timing_t	I²C Fast Mode Plus timing for SCL
Cscl_fast_mode_timing_t	I²C Fast Mode timing for SCL
Cscl_open_drain_timing_t	I³C open-drain timing for SCL
Cscl_push_pull_timing_t	I³C push-pull timing for SCL
Csdio_cmd_config_t	SD Host command configuration structure
Csdio_config_t	SD Host initialization configuration structure
Csdio_data_config_t	The SD Host data transfer configuration structure
Csdio_sd_card_config_t	SD card configuration structure
Csdio_write_read_config_t	SD Host Write/Read structure
Cspi_config	SPI configuration structure
Cspi_xfer_config	SPI transfer configuration structure
Cspwm_config_t	Unified SPWM configuration structure
Cspwm_dsc_chain_status_t	Descriptor chain execution status
Cspwm_pwm_cfg_t	PWM mode configuration
Cspwm_pwmdt_cfg_t	PWM with Dead-Time configuration
Cspwm_pwmpr_cfg_t	PWM with Pseudo-Random configuration
Cspwm_quad_cfg_t	Quadrature decoder configuration
Cspwm_sr_cfg_t	Shift Register configuration
Cspwm_timer_cfg_t	Timer/Counter mode configuration
Cspwm_trigger_in_cfg_t	Input trigger configuration structure
Cuart_config_t	UART control configuration structure
Cuart_get_config_t	UART receive configuration structure
Cuart_hw_status_t	UART instance hardware status structure
Cuart_put_config_t	UART transmit configuration structure
Cuart_usr_lsr_status_bits_t	Combined UART USR (Status Register) and LSR (Line Status Register) bitfield