Clock Driver Sample Application

Description

The Clock Driver sample application demonstrates clock configuration and validation on the supported boards for this application. It performs comprehensive clock management operations including enabling clocks, checking status, reading clock rates and dividers, configuring PLL settings, and handling clock disable operations with proper error handling.

The sample includes multiple clock operations:

  • Clock enable: Enable CPU_CLK and verify the enable status.

  • Clock rate reading: Read the current clock frequency and divider values.

  • PLL configuration: Set PLL0 to CLK_PLL_CFG_HIGH and verify the active configuration.

  • Clock disable: Attempt to disable the clock while handling expected return conditions (busy/system-clock or children-enabled).

During each run, the app logs clock enable/disable status, configuration changes, rate measurements, and validation results. This makes it easy for end users to confirm that clock setup and API operations are working as expected.

The latest example structure uses a common application source tree with board-specific hardware setup kept under hw/<BOARD>/. For this app:

  • Common application sources such as main.c, clk_sample_app.c, and clk_sample_app.h stay in the app root.

  • Application defconfigs are stored under configs/.

  • Board and hardware-specific setup is selected from hw/<BOARD>/, for example hw/SR110_RDK/.

The application can also be exported and built as a standalone app repository. In that flow, keep this app in its own directory, point SRSDK_DIR to the SDK root, and build from the app directory itself. For the full application workflow model, see Astra MCU SDK User Guide.

Supported Boards

This application supports:

  • SR110_RDK

Select the defconfig that matches your target board, and the build system will pick the corresponding board-specific hardware setup from hw/<BOARD>/.

Prerequisites

Test Case Selection

Before building, choose the testcase defconfig that matches your target board.

You can:

  • Select the required defconfig directly from the application’s configs/ directory.

  • Run make list_defconfigs from the application directory to list all supported defconfigs.

Available defconfigs:

  • sr110_rdk_cm55_clk_sample_app_defconfig

Building and Flashing the Example using VS Code

Use the VS Code flow described in the respective soc vscode guides and the VS Code Extension guide:

Build (VS Code):

  1. Open Build and Deploy -> Build Configurations.

  2. Select the clk_sample_app project configuration in the Project Configuration dropdown.

  3. Build with Build (SDK+Project) for the first build, or Build (Project) for rebuilds.

Flash (VS Code):

  1. Use Image Conversion to generate the flash image.

  2. Use Image Flashing (SWD/JTAG) to flash the firmware image.

Building and Flashing the Example using CLI

Use the CLI flow described in the respective build guide:

Build (CLI):

  1. Build from the application directory itself:

    cd <sdk-root>/examples/driver_examples/clk_sample_app
export SRSDK_DIR=<sdk-root>
make <app_defconfig> BUILD=SRSDK

  2. For faster rebuilds when only app code changes, reuse the app-local installed SDK package:

    cd <sdk-root>/examples/driver_examples/clk_sample_app
export SRSDK_DIR=<sdk-root>
make build

  3. If this app has been exported to its own repository, use the same commands from that exported app directory after setting SRSDK_DIR to the SDK root.

Build outputs (CLI):

  • Application binary: <app-dir>/out/<target>/release/<target>.elf

  • App-local SDK package: <app-dir>/install/<BOARD>/<BUILD_TYPE>/

Flash (CLI):

  1. Activate the SDK venv (required for image generation tools):

    # Linux/macOS
source <sdk-root>/.venv/bin/activate
# Windows PowerShell
.\.venv\Scripts\Activate.ps1

  2. Generate the flash image:

    cd <sdk-root>/tools/srsdk_image_generator
python srsdk_image_generator.py \
  -B0 \
  -flash_image \
  -sdk_secured \
  -spk "<sdk-root>/tools/srsdk_image_generator/Inputs/spk_rc4_1_0_secure_otpk.bin" \
  -apbl "<sdk-root>/tools/srsdk_image_generator/Inputs/sr100_b0_bootloader_ver_0x012F_ASIC.axf" \
  -m55_image "<sdk-root>/examples/driver_examples/clk_sample_app/out/sr110_cm55_fw/release/sr110_cm55_fw.elf" \
  -flash_type "GD25LE128" \
  -flash_freq "67"

  3. Flash the firmware image:

    cd <sdk-root>
python tools/openocd/scripts/flash_xspi_tcl.py \
  --cfg_path tools/openocd/configs/sr110_m55.cfg \
  --image tools/srsdk_image_generator/Output/B0_Flash/B0_flash_full_image_GD25LE128_67Mhz_secured.bin \
  --erase-all

Running the Application using VS Code Extension

  1. Press RESET on the board after flashing.

  2. For logging output, click SERIAL MONITOR and connect to the DAP logger port on J14.

    • To make it easier to identify, ensure only J14 is plugged in (not J13).

    • The logger port is not guaranteed to be consistent across OSes. As a starting point:

      • Windows: try the lower-numbered J14 COM port first.

      • Linux/macOS: try the higher-numbered J14 port first.

    • If you do not see logs after a reset, switch to the other J14 port.

  3. Clock sample logs appear in the logger window, including clock operations and validation results.

Expected Logs

0391468933:[0][WRN][LOGR]:Changing logger interface to LOGGER_IF_UART_1
0000000023:[0][INF][SYS ]:Application drivers initialization complete without errors.
0000004203:[0][INF][SYS ]:sr110 SDK version 1.3.0
0000006678:[0][INF][CLK ]:Clock 11 enabled.
0000008898:[0][INF][CLK ]:Clock 11 is ENABLED
0000011212:[0][INF][CLK ]:Clock 11 current rate: 400000000 Hz
0000014290:[0][INF][CLK ]:Clock 11 divider: 1
0000016615:[0][INF][CLK ]:PLL 0 config set to HIGH
0000019167:[0][INF][CLK ]:PLL 0 current config: 5
0000021674:[0][INF][CLK ]:Clock 11 disabled successfully.
0000024559:[0][INF][CLK ]:Clock test completed.