Clock Driver Sample Application

Description

The Clock Driver sample application runs a focused validation sequence on CPU_CLK using CLK_PLL0. It enables the clock, checks enable status, reads the current clock rate and divider, sets PLL0 to CLK_PLL_CFG_HIGH, reads back the active PLL configuration, and then attempts to disable the clock while handling expected return paths (for example, busy/system-clock or children-enabled conditions). Each step logs pass/fail status and returned values through the logger for quick API-level verification on SR110.

Prerequisites

Choose one setup path:
- CLI: Setup and Install SDK using CLI
- VS Code: Setup and Install SDK using VS Code

Building and Flashing the Example using VS Code

Use the VS Code flow described in the SR110 guide and the VS Code Extension guide:

Build (VS Code):

Open Build and Deploy -> Build Configurations.
Select clk_sample_app in the Application dropdown.
Build with Build (SDK + App) for the first build, or Build App for rebuilds.

Flash (VS Code):

Use Image Conversion to generate the flash image.
Use Image Flashing (SWD/JTAG) to flash the firmware image.

Building and Flashing the Example using CLI

Use the CLI flow described in the SR110 guide:

SR110 Build and Flash with CLI

Build (CLI):

From <sdk-root>/examples, build the example:

cd <sdk-root>/examples
export SRSDK_DIR=<sdk-root>
make cm55_clk_sample_app_defconfig BOARD=SR110_RDK BUILD=SRSDK

Flash (CLI):

Activate the SDK venv (required for image generation tools):

# Linux/macOS
source <sdk-root>/.venv/bin/activate
# Windows PowerShell
.\.venv\Scripts\Activate.ps1

Generate the flash image:

cd <sdk-root>/tools/srsdk_image_generator
python srsdk_image_generator.py \
  -B0 \
  -flash_image \
  -sdk_secured \
  -spk "<sdk-root>/tools/srsdk_image_generator/B0_Input_examples/spk_rc4_1_0_secure_otpk.bin" \
  -apbl "<sdk-root>/tools/srsdk_image_generator/B0_Input_examples/sr100_b0_bootloader_ver_0x012F_ASIC.axf" \
  -m55_image "<sdk-root>/examples/out/sr110_cm55_fw/release/sr110_cm55_fw.elf" \
  -flash_type "GD25LE128" \
  -flash_freq "67"

Flash the firmware image:

cd <sdk-root>
python tools/openocd/scripts/flash_xspi_tcl.py \
  --cfg_path tools/openocd/configs/sr110_m55.cfg \
  --image tools/srsdk_image_generator/Output/B0_Flash/B0_flash_full_image_GD25LE128_67Mhz_secured.bin \
  --erase-all

Running the Application using VS Code Extension

Press RESET on the board after flashing.
For logging output, click SERIAL MONITOR and connect to the DAP logger port on J14.
- To make it easier to identify, ensure only J14 is plugged in (not J13).
- The logger port is not guaranteed to be consistent across OSes. As a starting point:
  - Windows: try the lower-numbered J14 COM port first.
  - Linux/macOS: try the higher-numbered J14 port first.
- If you do not see logs after a reset, switch to the other J14 port.
Clock sample logs appear in the logger window.

Expected Logs

0391468933:[0][WRN][LOGR]:Changing logger interface to LOGGER_IF_UART_1
0000000023:[0][INF][SYS ]:Application drivers initialization complete without errors.
0000004203:[0][INF][SYS ]:sr110 SDK version 1.3.0
0000006678:[0][INF][CLK ]:Clock 11 enabled.
0000008898:[0][INF][CLK ]:Clock 11 is ENABLED
0000011212:[0][INF][CLK ]:Clock 11 current rate: 400000000 Hz
0000014290:[0][INF][CLK ]:Clock 11 divider: 1
0000016615:[0][INF][CLK ]:PLL 0 config set to HIGH
0000019167:[0][INF][CLK ]:PLL 0 current config: 5
0000021674:[0][INF][CLK ]:Clock 11 disabled successfully.
0000024559:[0][INF][CLK ]:Clock test completed.